It is reported that TSMC’s board of directors has recently passed the decision to build an advanced packaging and testing plant in Zhunan, which is located at Zhunan Science Park in Miaoli County. The packaging and testing plant is expected to have a total investment of approximately RMB 71.62 billion, and it plans to operate the first phase of the production area in the middle of next year. In addition to TSMC, SMIC has also established a joint factory with Changjiang Electronics Technology to deploy wafer-level packaging. What is the motivation for TSMC to lay out advanced packaging? Fab manufacturers continue to increase the packaging industry, what impact will it have on the competition and cooperation between the upstream and downstream of the industry chain?
Leading wafer level packaging
TSMC is not only a leading global foundry company, but also a leader in wafer-level packaging. After a decade or so of layout, TSMC has formed a wafer-level system integration platform including CoWoS (wafer-on-substrate packaging), InFO (integrated fan-out packaging), and SoIC (system integration single chip packaging).
TSMC’s packaging technology focuses on wafer-level packaging solutions. Compared with packaging in the general sense, the biggest feature of wafer-level packaging is "sealing before cutting." According to Applied Materials, wafer-level packaging is to package chips on a wafer instead of cutting the wafer into individual chips and then packaging. This solution can achieve greater bandwidth, higher speed, higher reliability and lower power consumption.
CoWoS is the first wafer-level packaging product launched by TSMC, and was first applied to 28nm FPGA packaging in 2012. CoWoS can achieve denser chip stacking and is suitable for the high-performance computing market with high connection density and large package size. With the explosion of AI chips, CoWoS has become a powerful weapon for TSMC to attract high-performance computing customers. Its derivative versions are used in Nvidia's Pascal, Volta series, AMD Vega, Intel Spring Crest and other chip products.
The InFO package is the key to TSMC's ability to stand out from the competition with Samsung and win Apple's large order. InFO cancels the use of carrier boards, which can meet the high pin count and thin packaging requirements of smart phone chips, and subsequent versions are suitable for a wider range of scenarios. Tuo Dai Industry Research Institute pointed out that InFO-oS is mainly for high-performance computing, InFO-MS is for servers and storage, and InFO-AiP technology is the mainstream for 5G communication packaging.
On the basis of InFO and CoWoS, TSMC continues to develop 3D packaging. At the Japan VLSI Technology and Circuit Seminar held in June 2019, TSMC proposed a new type of SoIC package to further increase the overall computing speed between the CPU/GPU processor and the memory, and it is expected to achieve mass production in 2021.
There are two reasons why TSMC can develop the packaging business and even lead the development of wafer-level packaging. On the one hand, wafer-level packaging emphasizes the cooperation with wafer manufacturing, and TSMC has long-term technology accumulation in wafer manufacturing, which is conducive to the development of packaging technology that meets the needs. At the same time, TSMC’s own wafer output can support the amount of packaging technology and increase the input-output ratio of packaging development. On the other hand, TSMC has the advantages of talents and capital based on its position as a leading foundry.
"With its position in the industry, TSMC can gather the world's top packaging and testing talents, and in terms of development financial resources, it is more assured than ordinary packaging and testing companies." An analyst told reporters.
Create a one-stop service
In the fourth quarter of 2017, TSMC stated that its CoWoS is used for HPC applications, especially in the fields of AI, data services and networking, and is mainly produced in conjunction with the 16nm process; InFO technology is mainly used for smartphone chips, and HPC and smartphones are the two major sources of TSMC's revenue in 2017, of which smartphone business revenue accounted for 50%, and HPC accounted for 25%.
It is not difficult to see that TSMC's packaging layout belongs to the "supporting business" of foundry, and the main goal is to form differentiated competition with other foundry manufacturers.
"Packaging and wafer manufacturing are both indispensable links in chip production. With the development and evolution of technology, the importance of packaging has continued to increase and has become one of the core competitiveness of foundries." The analyst told "China "Electronic News" reporter said, "Therefore, TSMC continues to increase the development of process technology near wafer manufacturing in packaging to provide a more complete one-stop solution."
TrendForce Consulting analyst Wang Zunmin pointed out to reporters that the main reason for TSMC’s entry into the packaging and testing field is to extend its advanced process technology. Through the manufacture of high-end CPU, GPU, and FPGA chips, and provide corresponding packaging and testing processes to provide complete "Manufacturing + packaging and testing" solutions.
"Although the fab needs additional R&D expenses such as packaging and testing, this solution can effectively attract high-end chip design companies to place orders and realize the business model of'manufacturing first, packaging and testing supplemented'." Wang Zunmin said.
At the same time, in the post-Moore era, the manufacturing process is approaching its limit, and packaging is of great significance to the continuation of Moore's Law, which has attracted more and more attention from integrated circuit manufacturers.
"The essence of Moore's Law is to integrate more transistors per unit area. As Moore's Law slows down, manufacturers need to work hard on packaging and integrate more transistors per unit area through stacking or other methods." Industry veteran Sheng Ling Haixiang The reporter said.
"Advanced packaging and testing is the growth point of the semiconductor industry in the future. The market prospects are broad. Accelerating the promotion of advanced packaging and testing layout can win the long-term voice of the semiconductor market." Analyst Wang Ruoda pointed out to reporters, "Entering the advanced packaging and testing market has a higher Capital and technology thresholds, TSMC can quickly seize the market by relying on years of accumulation of capital and technology."
High-end market for packaging and testing companies is squeezed
In addition to TSMC, SMIC is also deploying wafer-level packaging based on cooperation with Changjiang Electronics Technology. In 2014, SMIC and Changjiang Electronics Technology jointly established SMIC Changjiang Electronics, focusing on mid-range silicon wafer manufacturing and testing services and 3D system integration chip business. In 2019, SMIC released the ultra-wideband dual-polarized 5G millimeter wave antenna chip wafer-level integrated package SmartAiP, which realized 24GHz to 43GHz ultra-wideband signal transmission and reception, which will help further realize the ability of RF front-end module integrated packaging. .
"The future development direction of packaging and testing may no longer be limited to the previous individual foundry links, but an integrated solution that combines design, materials, and equipment. The development trend of integrated circuit front and back process integration is becoming increasingly obvious." Wang Ruoda said.
Head manufacturers continue to strengthen the layout of wafer-level packaging, will it affect the competition and cooperation between wafer and packaging?
Wang Ruoda said that the emergence of wafer-level packaging has blurred the boundaries between fabs and packaging and testing plants. Foundry companies have begun to squeeze the packaging and testing enterprise space and directly enter high-end packaging and testing.
Sheng Linghai also pointed out that there used to be a complete division of labor between packaging plants and foundries, but in high-end scenarios, fabs had to develop corresponding wafer-level packaging technologies on their own, and packaging and testing plants should maintain corresponding levels in high-end scenarios. Competitiveness also requires corresponding craftsmanship.
TSMC and other wafer manufacturers are competing with packaging and testing plants in the high-end market, and they also put forward requirements for the technology research and development capabilities and order-corresponding capabilities of packaging and testing plants.
"TSMC’s investment in high-end packaging and testing will compress a small part of the high-end market of packaging and testing foundries. However, for packaging and testing foundries, the main market is still in other consumer electronics products. In addition to being active In addition to developing high-end packaging and testing technology to attract customers, it will be more important to consolidate the source of orders from other wafer fabs." Wang Zunmin said.